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git://git.code.sf.net/p/sbcl/sbcl
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x86-64: add AVX-512CD, AVX-512VNNI, and AVX-512BF16 instruction definitions
This commit is contained in:
Aaron Estrada
Stas Boukarev
parent
94f65cecd8
commit
0546c92588
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@ -3,8 +3,9 @@
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;;;; AVX-512 Instruction Support
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;;;;
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;;;; Implemented subsets:
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;;;; AVX-512F, AVX-512BW, AVX-512DQ, AVX-512IFMA,
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;;;; AVX-512F, AVX-512BW, AVX-512DQ, AVX-512CD, AVX-512IFMA,
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;;;; AVX-512VBMI, AVX-512VBMI2, AVX-512VPOPCNTDQ, AVX-512BITALG,
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;;;; AVX-512VNNI, AVX-512BF16,
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;;;; GFNI (in avx2-insts.lisp),
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;;;; VPCLMULQDQ-256/512 (via VEX auto-promotion to EVEX),
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;;;; EVEX Compare-to-Opmask (vcmpps, vcmppd, vcmpss, vcmpsd),
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@ -14,12 +15,9 @@
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;;;; EVEX Gather & Scatter (vpgather*, vgather*, vpscatter*, vscatter*).
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;;;;
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;;;; Not yet implemented / Future extensions:
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;;;; AVX-512CD - vpconflictd/q, vplzcntd/q
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;;;; AVX-512VL - Explicit EVEX 128/256-bit forms with masking/broadcast
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;;;; (auto-promotion handles basic ZMM; full VL needs
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;;;; explicit EVEX for XMM/YMM with masking)
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;;;; AVX-512VNNI - vpdpbusd/s, vpdpwssd/s (Neural network integer dot products)
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;;;; AVX-512BF16 - vcvtne2ps2bf16, vcvtneps2bf16, vdpbf16ps (Bfloat16)
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;;;; AVX-512FP16 - Half-precision FP16 arithmetic (~100 instructions)
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;;;; VAES-256/512 - Wide forms of vaesenc/vaesdec
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;;;; VP2INTERSECT - vp2intersectd/q
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@ -1325,3 +1323,224 @@
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(def vscatterdps-z #xa2 0)
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(def vpscatterdq-z #xa0 1)
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(def vscatterdpd-z #xa2 1))
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;;;; ---- AVX-512CD instructions ----
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;;; Conflict detection (2-operand)
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(macrolet ((def (name opcode w)
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`(define-instruction ,name (segment dst src)
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,@(avx512-inst-printer-list 'ymm-ymm/mem #x66 opcode
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:opcode-prefix #x0f38 :w w)
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(:emitter
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(emit-avx512-inst segment src dst #x66 ,opcode
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:opcode-prefix #x0f38
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:w ,w
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:disp-n (full-vector-disp-n dst))))))
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(def vpconflictd #xc4 0)
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(def vpconflictq #xc4 1)
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(def vplzcntd #x44 0)
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(def vplzcntq #x44 1))
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;;; Conflict detection with opmask
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(macrolet ((def (name opcode w)
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`(define-instruction ,name (segment dst src mask &optional (zeroing 0))
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,@(loop for k from 1 to 7
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem #x66 opcode
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:opcode-prefix #x0f38
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:w w
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:more-fields `((aaa ,k) (z-bit 0))
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:printer '(:name :tab reg ", " reg/mem " {" aaa "}"))
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem #x66 opcode
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:opcode-prefix #x0f38
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:w w
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:more-fields `((aaa ,k) (z-bit 1))
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:printer '(:name :tab reg ", " reg/mem " {" aaa "} {z}")))
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(:emitter
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(let ((mask-num (cond ((integerp mask) mask)
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((k-register-p mask) (reg-id-num (reg-id mask)))
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(t (error "Invalid mask ~S" mask))))
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(z-num (if (or (eq zeroing :z) (eql zeroing 1)) 1 0)))
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(emit-avx512-inst segment src dst #x66 ,opcode
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:opcode-prefix #x0f38
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:w ,w
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:aaa mask-num
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:z z-num
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:disp-n (full-vector-disp-n dst)))))))
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(def vpconflictd-masked #xc4 0)
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(def vpconflictq-masked #xc4 1)
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(def vplzcntd-masked #x44 0)
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(def vplzcntq-masked #x44 1))
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;;; Broadcast mask bit to vector register
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(macrolet ((def (name opcode w)
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`(define-instruction ,name (segment dst src)
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,@(avx512-inst-printer-list 'ymm-ymm/mem #xf3 opcode
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:opcode-prefix #x0f38 :w w)
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(:emitter
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(emit-avx512-inst segment src dst #xf3 ,opcode
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:opcode-prefix #x0f38
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:w ,w)))))
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(def vpbroadcastmb2q #x2a 1)
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(def vpbroadcastmw2d #x3a 0))
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;;;; ---- AVX-512VNNI instructions ----
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;;; Vector Neural Network Instructions (3-operand NDS)
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(macrolet ((def (name opcode)
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`(define-instruction ,name (segment dst src1 src2)
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,@(avx512-inst-printer-list 'ymm-ymm/mem #x66 opcode
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:opcode-prefix #x0f38 :w 0 :nds t)
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(:emitter
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(emit-avx512-inst segment src2 dst #x66 ,opcode
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:opcode-prefix #x0f38
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:vvvv src1
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:w 0
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:disp-n (full-vector-disp-n dst))))))
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(def vpdpbusd #x50)
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(def vpdpbusds #x51)
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(def vpdpwssd #x52)
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(def vpdpwssds #x53))
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;;; Vector Neural Network Instructions with opmask
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(macrolet ((def (name opcode)
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`(define-instruction ,name (segment dst src1 src2 mask &optional (zeroing 0))
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,@(loop for k from 1 to 7
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem #x66 opcode
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:opcode-prefix #x0f38
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:w 0
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:nds t
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:more-fields `((aaa ,k) (z-bit 0))
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:printer '(:name :tab reg ", " vvvv ", " reg/mem " {" aaa "}"))
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem #x66 opcode
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:opcode-prefix #x0f38
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:w 0
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:nds t
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:more-fields `((aaa ,k) (z-bit 1))
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:printer '(:name :tab reg ", " vvvv ", " reg/mem " {" aaa "} {z}")))
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(:emitter
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(let ((mask-num (cond ((integerp mask) mask)
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((k-register-p mask) (reg-id-num (reg-id mask)))
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(t (error "Invalid mask ~S" mask))))
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(z-num (if (or (eq zeroing :z) (eql zeroing 1)) 1 0)))
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(emit-avx512-inst segment src2 dst #x66 ,opcode
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:opcode-prefix #x0f38
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:vvvv src1
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:w 0
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:aaa mask-num
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:z z-num
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:disp-n (full-vector-disp-n dst)))))))
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(def vpdpbusd-masked #x50)
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(def vpdpbusds-masked #x51)
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(def vpdpwssd-masked #x52)
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(def vpdpwssds-masked #x53))
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;;;; ---- AVX-512BF16 instructions ----
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;;; Convert two single-precision vectors to bfloat16 (3-operand NDS)
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(macrolet ((def (name opcode prefix)
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`(define-instruction ,name (segment dst src1 src2)
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,@(avx512-inst-printer-list 'ymm-ymm/mem prefix opcode
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:opcode-prefix #x0f38 :w 0 :nds t)
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(:emitter
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(emit-avx512-inst segment src2 dst ,prefix ,opcode
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:opcode-prefix #x0f38
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:vvvv src1
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:w 0
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:disp-n (full-vector-disp-n dst))))))
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(def vcvtne2ps2bf16 #x72 #xf2)
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(def vdpbf16ps #x52 #xf3))
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;;; 3-operand BF16 with opmask
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(macrolet ((def (name opcode prefix)
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`(define-instruction ,name (segment dst src1 src2 mask &optional (zeroing 0))
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,@(loop for k from 1 to 7
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem prefix opcode
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:opcode-prefix #x0f38
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:w 0
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:nds t
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:more-fields `((aaa ,k) (z-bit 0))
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:printer '(:name :tab reg ", " vvvv ", " reg/mem " {" aaa "}"))
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem prefix opcode
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:opcode-prefix #x0f38
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:w 0
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:nds t
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:more-fields `((aaa ,k) (z-bit 1))
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:printer '(:name :tab reg ", " vvvv ", " reg/mem " {" aaa "} {z}")))
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(:emitter
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(let ((mask-num (cond ((integerp mask) mask)
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((k-register-p mask) (reg-id-num (reg-id mask)))
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(t (error "Invalid mask ~S" mask))))
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(z-num (if (or (eq zeroing :z) (eql zeroing 1)) 1 0)))
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(emit-avx512-inst segment src2 dst ,prefix ,opcode
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:opcode-prefix #x0f38
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:vvvv src1
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:w 0
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:aaa mask-num
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:z z-num
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:disp-n (full-vector-disp-n dst)))))))
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(def vcvtne2ps2bf16-masked #x72 #xf2)
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(def vdpbf16ps-masked #x52 #xf3))
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;;; Convert single-precision vector to bfloat16 (2-operand)
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(macrolet ((def ()
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`(define-instruction vcvtneps2bf16 (segment dst src)
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,@(avx512-inst-printer-list 'ymm-ymm/mem #xf3 #x72
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:opcode-prefix #x0f38 :w 0)
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(:emitter
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(let ((ll (cond ((or (zmm-register-p src) (ymm-register-p dst)) #b10)
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((ymm-register-p src) #b01)
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(t #b00)))
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(disp-n (if (or (zmm-register-p src) (ymm-register-p dst)) 64 (full-vector-disp-n dst))))
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(emit-avx512-inst segment src dst #xf3 #x72
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:opcode-prefix #x0f38
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:w 0
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:ll ll
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:disp-n disp-n))))))
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(def))
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(macrolet ((def ()
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`(define-instruction vcvtneps2bf16-masked (segment dst src mask &optional (zeroing 0))
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,@(loop for k from 1 to 7
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem #xf3 #x72
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:opcode-prefix #x0f38
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:w 0
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:more-fields `((aaa ,k) (z-bit 0))
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:printer '(:name :tab reg ", " reg/mem " {" aaa "}"))
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append
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(avx512-inst-printer-list
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'ymm-ymm/mem #xf3 #x72
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:opcode-prefix #x0f38
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:w 0
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:more-fields `((aaa ,k) (z-bit 1))
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:printer '(:name :tab reg ", " reg/mem " {" aaa "} {z}")))
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(:emitter
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(let ((mask-num (cond ((integerp mask) mask)
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((k-register-p mask) (reg-id-num (reg-id mask)))
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(t (error "Invalid mask ~S" mask))))
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(z-num (if (or (eq zeroing :z) (eql zeroing 1)) 1 0))
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(ll (cond ((or (zmm-register-p src) (ymm-register-p dst)) #b10)
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((ymm-register-p src) #b01)
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(t #b00)))
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(disp-n (if (or (zmm-register-p src) (ymm-register-p dst)) 64 (full-vector-disp-n dst))))
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(emit-avx512-inst segment src dst #xf3 #x72
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:opcode-prefix #x0f38
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:w 0
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:ll ll
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:aaa mask-num
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:z z-num
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:disp-n disp-n))))))
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(def))
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@ -374,5 +374,47 @@
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(test-assemble `(vaddps-masked ,zmm0 ,zmm1 ,zmm2 ,k1 :z)
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"62F174C958C2 VADDPS-MASKED ZMM0, ZMM1, ZMM2 {K1} {z}")
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(try `(vdivps-masked ,zmm0 ,zmm1 ,zmm2 ,k1))
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(try `(vsqrtps-masked ,zmm0 ,zmm1 ,k1))))
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(try `(vsqrtps-masked ,zmm0 ,zmm1 ,k1))
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;; AVX-512CD (Conflict Detection)
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(test-assemble `(vpconflictd ,zmm0 ,zmm1)
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"62F27D48C4C1 VPCONFLICTD ZMM0, ZMM1")
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(test-assemble `(vpconflictq ,zmm0 ,zmm1)
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"62F2FD48C4C1 VPCONFLICTQ ZMM0, ZMM1")
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(test-assemble `(vplzcntd ,zmm0 ,zmm1)
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"62F27D4844C1 VPLZCNTD ZMM0, ZMM1")
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(test-assemble `(vplzcntq ,zmm0 ,zmm1)
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"62F2FD4844C1 VPLZCNTQ ZMM0, ZMM1")
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(test-assemble `(vpconflictd-masked ,zmm0 ,zmm1 ,k1 :z)
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"62F27DC9C4C1 VPCONFLICTD-MASKED ZMM0, ZMM1 {K1} {z}")
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(test-assemble `(vplzcntd-masked ,zmm0 ,zmm1 ,k1)
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"62F27D4944C1 VPLZCNTD-MASKED ZMM0, ZMM1 {K1}")
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(try `(vpbroadcastmb2q ,zmm0 ,k1))
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(try `(vpbroadcastmw2d ,zmm0 ,k1))
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;; AVX-512VNNI (Vector Neural Network Instructions)
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(test-assemble `(vpdpbusd ,zmm0 ,zmm1 ,zmm2)
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"62F2754850C2 VPDPBUSD ZMM0, ZMM1, ZMM2")
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(test-assemble `(vpdpbusds ,zmm0 ,zmm1 ,zmm2)
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"62F2754851C2 VPDPBUSDS ZMM0, ZMM1, ZMM2")
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(test-assemble `(vpdpwssd ,zmm0 ,zmm1 ,zmm2)
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"62F2754852C2 VPDPWSSD ZMM0, ZMM1, ZMM2")
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(test-assemble `(vpdpwssds ,zmm0 ,zmm1 ,zmm2)
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"62F2754853C2 VPDPWSSDS ZMM0, ZMM1, ZMM2")
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(test-assemble `(vpdpbusd-masked ,zmm0 ,zmm1 ,zmm2 ,k1 :z)
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"62F275C950C2 VPDPBUSD-MASKED ZMM0, ZMM1, ZMM2 {K1} {z}")
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;; AVX-512BF16 (Bfloat16 Operations)
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(test-assemble `(vcvtne2ps2bf16 ,zmm0 ,zmm1 ,zmm2)
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"62F2774872C2 VCVTNE2PS2BF16 ZMM0, ZMM1, ZMM2")
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(test-assemble `(vcvtne2ps2bf16-masked ,zmm0 ,zmm1 ,zmm2 ,k1 :z)
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"62F277C972C2 VCVTNE2PS2BF16-MASKED ZMM0, ZMM1, ZMM2 {K1} {z}")
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(test-assemble `(vcvtneps2bf16 ,ymm0 ,zmm1)
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"62F27E4872C1 VCVTNEPS2BF16 ZMM0, ZMM1")
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(test-assemble `(vcvtneps2bf16-masked ,ymm0 ,zmm1 ,k1 :z)
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"62F27EC972C1 VCVTNEPS2BF16-MASKED ZMM0, ZMM1 {K1} {z}")
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(test-assemble `(vdpbf16ps ,zmm0 ,zmm1 ,zmm2)
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"62F2764852C2 VDPBF16PS ZMM0, ZMM1, ZMM2")
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(test-assemble `(vdpbf16ps-masked ,zmm0 ,zmm1 ,zmm2 ,k1 :z)
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"62F276C952C2 VDPBF16PS-MASKED ZMM0, ZMM1, ZMM2 {K1} {z}")))
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