* use a loopless final pass after the unrolled pass
* use one fewer temp register
* remove a couple of instructions here and there
Also some stylistic changes:
* give better names to registers depending on their usage
* avoid an #ifdef for SB_SAFEPOINT in x86-64-arch
Co-authored with Gemini
* Add dstate-disp-n to disassem-state
* Add reg/mem arg types for tuple sizes 1,2,4,8,16,32,64.
* Extend avx512-inst-printer-list to accept :disp-n.
* Scale EVEX disp8 by the instruction-specific tuple size in decode-mod-r/m
* Annotate full-vector EVEX moves and emit compressed displacement for them.
* Add disassembler tests for the functionality in this patch
This covers the full-vector move subset. For other EVEX memory
instructions more work is needed.
* Add +evex+ indicator to distinguish EVEX from VEX/legacy
even for EVEX L'L=00 forms
* Decode ModRM.reg registers 16–31 using R'
* Stop incorrectly applying R' to ModRM.r/m operands
* Decode EVEX ModRM.r/m register-direct 16–31 using X as B'
* Decode EVEX vvvv registers 16–31 using V'
* add simd-pack-512-mask as intrinsic type (widetag)
* add associated book-keeping in VM, compiler and interpreter for simd-pack-512-mask
* add VM support for mask registers (mask-reg SC, SB, defregs, ...)
* add VOPs to compiler backend for construction, extraction
* add VOPs for movement: kregs<->kregs, kregs<->gpr and kregs<->mem
* add support for assembler in insts, avx2-insts and avx512-insts
* rewrite most of evex emitter regarding mask registers
* add print support in evex for mask related instructions
* fix some smaller bugs in previous simd-pack-512 support patch
* add tests for creation, extraction, movements, assembly printing and some internal functions
* refactor zmm-registers-used-p into avx512-state-used-p and update call sites
* add support for mask regs to avx512-state-used-p
If RDX ceases to be the first arg-passing register, then this test will fail
because there is no byte-sized register corresponding to byte index 1 of RDI.
I want to permute the 3 lisp arg-passing registers to match the machine ABI
and this change makes it less ugly to do so. (Some DEFINE-ALIEN-ROUTINEs
in user code and SBCL itself could potentially emit fewer moves by matching
the ABI but we also will want to tackle a problem of needless spill/restore
of register args by eliminating dead stores)
Other backends don't strictly benefit from this syntax because register
names such as A0,A1 already express exactly what they mean to, whereas x86
register names are alphabet soup in comparison.
We can safely assume n-fixnum-tag-bits = 1. Revision a369686d which gave 1 more
bit of precision theorized that a build-time choice could be made within a
particular backend. While that was true for a while after the commit, x86-64
is now so ingrained with the belief that fixnums are 63 bits that it can't
reasonably be changed. While we should prefer the symbolic constant in lieu
of a literal 1, that style does not imply that littering up the source with
illegible "#+#.(cl:if)" around vops that can't be enabled is sound practice.
The initial problem is that elt derives types on constant lists
without adding a NIL, which can be returned by NTH.
Always check bounds instead.
There's no performance advantage in not signaling an error.
This wasn't working right, and the assertion in LAYOUT-ID about assigning
only structures an ID was written incorrectly.
* Layout IDs are assigned only when applying a :layout-id fixup or when storing
into a descendant type's ID array, whichever occurs first.
* IDs of non-structure instances like STREAM that have nonzero IDs are
stored at the correct place for their depthoid, and not always at index 0
so that LAYOUT-ID doesn't have to test +structure-layout-flag+.
* LAYOUT-ID returns NIL instead of 0 if no ID is assigned.
machine-dependent files will never see the 0.
* The remark that IDs could do type-based dispatch is no longer hypothetical
